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.TH "IOSAPIC_LOAD_IRT" "9" "09 October 2005" "" ""

.SH NAME
iosapic_load_irt \- Fill in the interrupt routing table
.SH SYNOPSIS
"SYNOPSIS"
.sp
\fB
.sp
int __init iosapic_load_irt  (unsigned long \fIcell_num\fB, struct irt_entry ** \fIirt\fB);
\fR
.SH "ARGUMENTS"
.TP
\fB\fIcell_num\fB\fR
The cell number of the CPU we're currently executing on
.TP
\fB\fIirt\fB\fR
The address to place the new IRT at
\fIreturn\fR The number of entries found
.SH "DESCRIPTION"
.PP
The ``Get PCI INT Routing Table Size'' option returns the number of 
entries in the PCI interrupt routing table for the cell specified 
in the cell_number argument.  The cell number must be for a cell 
within the caller's protection domain.
.PP
The ``Get PCI INT Routing Table'' option returns, for the cell 
specified in the cell_number argument, the PCI interrupt routing 
table in the caller allocated memory pointed to by mem_addr.
We assume the IRT only contains entries for I/O SAPIC and
calculate the size based on the size of I/O sapic entries.
.PP
The PCI interrupt routing table entry format is derived from the
IA64 SAL Specification 2.4.   The PCI interrupt routing table defines
the routing of PCI interrupt signals between the PCI device output
``pins'' and the IO SAPICs' input ``lines'' (including core I/O PCI
devices).  This table does NOT include information for devices/slots
behind PCI to PCI bridges. See PCI to PCI Bridge Architecture Spec.
for the architected method of routing of IRQ's behind PPB's.