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[Music]

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all right well good afternoon welcome

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back after the break i was just uh

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watching the uh the logo thinking that

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um we should have a flipper sanitizer

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sayo

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so uh this next session is going to be

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talking about the various wares for the

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uh

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the rocklin swag bags and the party

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buttons so um

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this is the uh

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collection of hardware that we've been

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playing with throughout developing this

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project so we can see the old

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last year's swag badge we've got the new

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swag badge we've got um

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a various various rocklin prototypes in

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production and uh and there's no party

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button there

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um and so

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uh for those who are new to fpgas i'm

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going to dive in there's lots of

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terminology jargon but don't but don't

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let that put you off for playing of your

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rocklin um

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but at first they'll appear like a risk

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five processor just running c code um

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all the uh itc peripherals uh are

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controlled by c

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and uh and and all the and all the the

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cpu and uh the profiles appear on a

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memory map bus which you can just uh

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interact with directly from your laptop

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so you can basically peek and poke and

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send commands to see what's going on and

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as you get more gain more confidence you

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can

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dive in deeper into the into the world

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fpga tools and write down the individual

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gates

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so let's let's go

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so um

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we

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use uh use software to control hardware

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and typically that hardware has got

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specific functions it says it's either a

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cpu or a gpu uh it could be you know

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some sort of peripheral like an

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accelerometer and it's pretty hard for

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most of us to um create or change this

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these are these ics

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um

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yeah you need to be a large corporation

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and uh these ics may have some small

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number of gates maybe a dozen or so up

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to many billions of gates

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uh

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and uh and most of us who work we work

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in software

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uh

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throughout the hmc projects um you know

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when we're doing embedded um

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devices we use some firmware which is

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just a former software just takes a

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little bit longer to write a little bit

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longer to flash

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and a little bit harder to change

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so

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so this year with the fpjs we're uh

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we're going to be playing with gateway

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and so it's going to chat a little bit

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about what the gateway is

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so

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uh

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if fpgas which uh stands for fuel

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programmable gate array is a sort of the

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sort of ic that's um you know is

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programmable you can um you can change

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change of what changes function and it

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consists of a number quite a quite a few

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different parts

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the uh

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the the first three these main things

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are the uh what are called the lookup

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tables which allows you to do what's

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called combinational logic this is um

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uh

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sort of the the ands and the ors and not

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gates the uh logic logic gates um and

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what lookup table allows you to do is to

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have a number of inputs and a and

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typical single output and for any any

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combination of inputs you can define

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what that output is and it might use um

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a ram to just maintain uh create that

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lookup table

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but what combinational logic gates can't

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do is that they uh they don't allow you

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to um

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they're time independent so it doesn't

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matter um

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uh what any previous states are they

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always produce the same result

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so if you want to basically have

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a

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maintained state and have a different

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different results

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over time use a flip-flops these this is

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for doing sequential logic and you can

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maintain

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previous state and and uh and as

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you have new inputs you can your your

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output can depend upon a previous state

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and the other part we've got in fpga is

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what's called carry logic so if you've

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got a a number of cells yeah if you want

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to make like a shift register or

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something like that you can um

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chain the output from one cell to the to

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the next

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and so these

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logic cells are a combination of a

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lookup table

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flip-flop and the carry logic and on the

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fpga that we're using in the rockling

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you have about 5000 of those lookup

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tables

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the other thing a

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fpga has is the routing between logic

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cells

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you also have a

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clocks which um provide uh clocking

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clock signals out to all these cells to

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synchronize them

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and in the case of the fpga

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that's chosen is also a

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fair amount of memory you've got 128

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kilobytes of um of ram

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uh the other thing fpgas provides don't

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have to do everything um yourself in the

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in

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using your own the logic gates is you

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can get specialized circuits for doing

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um you know i2c or spi buses including

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digital signal processors for doing fast

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uh fast arithmetic

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and so what the gateway is it's the the

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it's the definition language allows you

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to describe your fpga and uh and then

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admin programming so this is what's

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called the gate the gateway

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so

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this is a this is a diagram from the uh

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the lattice documentation and you can

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see a logic still has these uh these

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components the lookup table

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the output lookup table goes to the flip

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flop and you also your carry logic and

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so you can you can see on the left hand

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side if you had eight souls in row you

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might you know create a shift register

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by having the carry logic trans transfer

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the output from one cell to the next

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so that's sort of a quick overview of

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what goes on goes on inside an fpga

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which i've kept track time

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uh so then once so if you want to

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basically uh

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define define what goes on in fpga and

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then and then flash or programming if

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fpga there's a open source tool chains

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now like for example uh symbiflow and so

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you start off with uh

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a uh a module description so it's like

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module.v in a hybrid description

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language like ferolog

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and it describes um

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all the combination logic and the um

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and the sequential logic and so on then

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how you want to use the different hard

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blocks and use a

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program called yosis which

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turns that

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high-level design into the

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actual logic gates

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then there's a program called next pnr

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which

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then places those logic gates

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into the various available resources of

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the fpga

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and then and then it routes the uh all

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those logic holes together

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and uh and then you then you need to

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create a what's called a bit stream

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which is a

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a configuration that's usually subject

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to the particular fpga chosen and and

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then finally

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the fpga

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we've chosen has a bootloader which

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allows it to appear as a usb device and

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there's a standard

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tool called dflutool diffuser which

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writes that bit stream to to the uh the

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rocklin fvga

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so that's the um the general

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process

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so so what so why have we chosen to use

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fpgas and why are other people excited

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about them given that most of the time

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we can just use um cpus and gpus and

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other other sorts of peripherals and uh

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don't even need to touch an fpga

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well if you're um

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if you're using something like a

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like an arduino um processors like that

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mega three to eight sometimes just you

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know just you know you run out of pwms

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or you just like to have another i2c bus

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or something like that and uh you don't

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and uh you don't have enough choice

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except to just choose another chip

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or um you know be really nice to um if

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there's an operation do really uh

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a lot and it's um the uh it's it's just

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slow to do in the uh instructions that

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you should be really nice to be able to

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like add another instruction or if you

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want to add

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uh you know a

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fpga html output and these are sort of

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things you can do uh quite easily in

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fpga

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uh and also if you can compare the

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performance of the uh these small

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microcontrollers

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um yeah they all have like a very

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similar price you know sort of like five

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dollars without 5k versus a couple

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dollars for that mega three two eight or

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a bit more for a for an stm

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32

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uh

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uh because the fha the choice has uh

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digital single processors you can if you

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have eight of those doing um 16-bit

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multipliers at 48 megahertz that's so

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that's a lot more horsepower than you do

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you get out of an at mega so

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so you've got these of um

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flexibility advantages

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and whilst we're we're playing it sort

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of at the very low end of the spectrum

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in terms of number of um

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uh lookup tables so it's only about 5000

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in the um in the up 5k they've chosen

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uh

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that's still that still allows you to do

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quite quite a bit so i'm comparing it to

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the

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original live 6502 microprocessor which

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had about three and a half thousand

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transistors there's more than enough uh

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lookup tables to um

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uh replicate the um function over 6502

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and so you can put a effectively put

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like a whole app or two inside this

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little up 5k or you could or even a a

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32-bit risk risk processor

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but just in comparison the other end of

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the spectrum

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a modern

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process like you'd find in your mac

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that's about nearly 60 billion

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transistors in that um similarly with a

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top-end gpu from uh from amd or even

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silence it's also around 60 billion uh

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transistors if you look at the um what

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you can get from an fpga it's um

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you know nearly a hundred hundred

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billion uh transistors so

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so even though we're only playing

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playing with uh a small number of gates

285
00:09:27,839 --> 00:09:32,959
in the uh with the rockling the same

286
00:09:29,920 --> 00:09:36,080
techniques would allow to

287
00:09:32,959 --> 00:09:38,160
acquire a very very large fpga and

288
00:09:36,080 --> 00:09:40,720
you could

289
00:09:38,160 --> 00:09:40,720
write your own

290
00:09:41,200 --> 00:09:44,800
modules to um you know utilize all those

291
00:09:43,040 --> 00:09:47,120
transistors for a very very custom job

292
00:09:44,800 --> 00:09:47,120
so you can

293
00:09:47,200 --> 00:09:50,480
apply apply the hard resources your

294
00:09:48,959 --> 00:09:51,920
transistors to exactly what i need and

295
00:09:50,480 --> 00:09:53,440
not waste them on anything you don't

296
00:09:51,920 --> 00:09:54,240
need

297
00:09:53,440 --> 00:09:55,279
so

298
00:09:54,240 --> 00:09:57,279
so what

299
00:09:55,279 --> 00:09:58,880
why should um we say take interest in

300
00:09:57,279 --> 00:10:01,040
fpgas now given they've been out since

301
00:09:58,880 --> 00:10:03,200
about 1985 so

302
00:10:01,040 --> 00:10:05,279
several decades and and one of the main

303
00:10:03,200 --> 00:10:06,880
reasons is that a lot of open source

304
00:10:05,279 --> 00:10:08,240
developers like uh by people like tim

305
00:10:06,880 --> 00:10:11,120
ansel have been pushing

306
00:10:08,240 --> 00:10:13,120
pushing very hard to um develop our open

307
00:10:11,120 --> 00:10:13,920
source tool chains and so

308
00:10:13,120 --> 00:10:15,440
uh

309
00:10:13,920 --> 00:10:18,000
it's becoming much

310
00:10:15,440 --> 00:10:19,440
much easier to use now so for decades uh

311
00:10:18,000 --> 00:10:21,920
the definition language like foreign log

312
00:10:19,440 --> 00:10:22,800
and vhdl were roughly like you know same

313
00:10:21,920 --> 00:10:25,440
sort of

314
00:10:22,800 --> 00:10:27,040
i guess abstraction as a writing c code

315
00:10:25,440 --> 00:10:29,839
and these were tied very close to

316
00:10:27,040 --> 00:10:32,000
proprietary tools um they were

317
00:10:29,839 --> 00:10:33,519
very slow sometimes with steep learning

318
00:10:32,000 --> 00:10:35,600
curves and that was fine if you're

319
00:10:33,519 --> 00:10:39,360
working in fpga you know day in day out

320
00:10:35,600 --> 00:10:42,079
as your main job but if you just want to

321
00:10:39,360 --> 00:10:43,920
you know have a bit of a play or um

322
00:10:42,079 --> 00:10:45,440
occasionally use it so it wasn't very

323
00:10:43,920 --> 00:10:47,279
attractive

324
00:10:45,440 --> 00:10:49,120
these days you can use

325
00:10:47,279 --> 00:10:51,519
high-level languages

326
00:10:49,120 --> 00:10:54,959
python in particular but also scala and

327
00:10:51,519 --> 00:10:57,120
others to define your fpga logic uh in

328
00:10:54,959 --> 00:10:59,279
your using a higher level language so

329
00:10:57,120 --> 00:11:00,560
you're not not so down

330
00:10:59,279 --> 00:11:03,120
you know

331
00:11:00,560 --> 00:11:05,279
at the low level the uh logic gates and

332
00:11:03,120 --> 00:11:06,800
there's um also additional software like

333
00:11:05,279 --> 00:11:09,920
litex which allows you to do whole

334
00:11:06,800 --> 00:11:13,839
components um so like a whole

335
00:11:09,920 --> 00:11:16,000
32-bit processor or um or a whole bus

336
00:11:13,839 --> 00:11:17,760
and uh and you can use this to uh

337
00:11:16,000 --> 00:11:20,240
connect together modular components so

338
00:11:17,760 --> 00:11:22,560
your cpu your controls and so on

339
00:11:20,240 --> 00:11:24,320
uh into uh into a quite high-level

340
00:11:22,560 --> 00:11:26,399
design it's much easier to use and

341
00:11:24,320 --> 00:11:28,000
there's um diagnosis tools like light

342
00:11:26,399 --> 00:11:29,839
scope which allows you to have a logic

343
00:11:28,000 --> 00:11:31,040
analyzer so it's become much more

344
00:11:29,839 --> 00:11:33,360
approachable

345
00:11:31,040 --> 00:11:34,480
um and even if you also find uh there's

346
00:11:33,360 --> 00:11:37,120
plenty of um

347
00:11:34,480 --> 00:11:37,760
uh existing verilog modules that or vhtl

348
00:11:37,120 --> 00:11:39,680
in

349
00:11:37,760 --> 00:11:41,760
in github or open cores you can still

350
00:11:39,680 --> 00:11:42,880
integrate those those into your into

351
00:11:41,760 --> 00:11:44,160
your design

352
00:11:42,880 --> 00:11:45,440
and so you can now pretty much work

353
00:11:44,160 --> 00:11:47,360
entirely in

354
00:11:45,440 --> 00:11:50,480
open source tool chains and

355
00:11:47,360 --> 00:11:52,480
for your fpga and often these tools are

356
00:11:50,480 --> 00:11:54,800
do synthesis much faster than the vendor

357
00:11:52,480 --> 00:11:54,800
tools

358
00:11:55,200 --> 00:12:00,399
so um so additional reasons why why

359
00:11:58,480 --> 00:12:02,000
perhaps you're interested is um it's uh

360
00:12:00,399 --> 00:12:03,920
even though you may not you know need to

361
00:12:02,000 --> 00:12:05,680
use the fpga very often very often it's

362
00:12:03,920 --> 00:12:07,440
so it's still very very capable thing to

363
00:12:05,680 --> 00:12:10,000
have you know to know how to do and it's

364
00:12:07,440 --> 00:12:11,279
also just fun um if you're into

365
00:12:10,000 --> 00:12:13,440
nostalgic

366
00:12:11,279 --> 00:12:15,120
hardware or you know dark video games or

367
00:12:13,440 --> 00:12:16,160
do your own cpu design

368
00:12:15,120 --> 00:12:18,560
there's something you can very easily

369
00:12:16,160 --> 00:12:20,399
play with uh with fpgas

370
00:12:18,560 --> 00:12:22,399
and so you know why i have to have the

371
00:12:20,399 --> 00:12:24,480
best of luck for all you use his asic

372
00:12:22,399 --> 00:12:26,160
cpus when you need to and

373
00:12:24,480 --> 00:12:27,360
and combine them with fpgas if that

374
00:12:26,160 --> 00:12:30,320
helps

375
00:12:27,360 --> 00:12:33,760
so so get so in terms of getting started

376
00:12:30,320 --> 00:12:35,200
um the up 5k is um it's fairly expensive

377
00:12:33,760 --> 00:12:36,959
it's a it's um

378
00:12:35,200 --> 00:12:38,880
offers a good range of um

379
00:12:36,959 --> 00:12:40,639
of capability and uh so

380
00:12:38,880 --> 00:12:43,519
tim ansel and uh

381
00:12:40,639 --> 00:12:45,279
uh his group his um colleagues uh

382
00:12:43,519 --> 00:12:47,920
produced the fomo a few years ago back

383
00:12:45,279 --> 00:12:49,360
in uh i think 2019 and there's also

384
00:12:47,920 --> 00:12:52,000
things like the icebreaker and now now

385
00:12:49,360 --> 00:12:54,240
this year produced the rockling

386
00:12:52,000 --> 00:12:55,680
tim's um workshop's a great great place

387
00:12:54,240 --> 00:12:58,399
to get started

388
00:12:55,680 --> 00:13:00,240
and uh and also hopefully first

389
00:12:58,399 --> 00:13:02,480
presentation give you give some more um

390
00:13:00,240 --> 00:13:04,720
some more insights

391
00:13:02,480 --> 00:13:04,720
so

392
00:13:04,959 --> 00:13:08,480
uh so so the inspiration for the

393
00:13:06,880 --> 00:13:10,720
rockling was um

394
00:13:08,480 --> 00:13:13,440
was that last year when we did the swag

395
00:13:10,720 --> 00:13:15,440
badge uh we didn't uh spend as much time

396
00:13:13,440 --> 00:13:16,480
on on sales as we

397
00:13:15,440 --> 00:13:18,079
would have liked we're hoping to

398
00:13:16,480 --> 00:13:20,320
encourage more people to um produce

399
00:13:18,079 --> 00:13:21,839
their own simple uh boards to add onto

400
00:13:20,320 --> 00:13:23,200
the swag badge

401
00:13:21,839 --> 00:13:24,880
and so we thought it'd be nice to try

402
00:13:23,200 --> 00:13:26,720
and create the um

403
00:13:24,880 --> 00:13:27,680
the most interesting so we could

404
00:13:26,720 --> 00:13:29,839
uh

405
00:13:27,680 --> 00:13:31,920
some some people have been chatting uh

406
00:13:29,839 --> 00:13:33,279
for a while about doing an fpga and we

407
00:13:31,920 --> 00:13:35,120
were long overdue

408
00:13:33,279 --> 00:13:37,440
due to a j project

409
00:13:35,120 --> 00:13:40,160
and so we start off with um

410
00:13:37,440 --> 00:13:42,079
uh some foamers that tim had provided

411
00:13:40,160 --> 00:13:45,199
and uh and saw that we were able to

412
00:13:42,079 --> 00:13:46,560
create uh the bootloader for it and so

413
00:13:45,199 --> 00:13:49,360
john

414
00:13:46,560 --> 00:13:51,360
3d printed a a rig so we could um flash

415
00:13:49,360 --> 00:13:53,920
our foamers with with faux boot and that

416
00:13:51,360 --> 00:13:55,680
that worked that was good and uh andy

417
00:13:53,920 --> 00:13:58,560
kitchen uh was

418
00:13:55,680 --> 00:14:00,320
also uh working with fpjs as part of as

419
00:13:58,560 --> 00:14:02,079
part of his work and so

420
00:14:00,320 --> 00:14:03,760
we just sort of had had all the right

421
00:14:02,079 --> 00:14:05,600
people you know bob had some some time

422
00:14:03,760 --> 00:14:08,480
to design and we think well what could

423
00:14:05,600 --> 00:14:12,000
we do with we um try to design our own

424
00:14:08,480 --> 00:14:12,880
uh fpga board and uh doing a playing of

425
00:14:12,000 --> 00:14:14,480
audio was something we hadn't done

426
00:14:12,880 --> 00:14:18,160
before so that seemed a natural thing to

427
00:14:14,480 --> 00:14:19,680
have with the the eight dsps and then uh

428
00:14:18,160 --> 00:14:20,959
and then to say what we're going to do

429
00:14:19,680 --> 00:14:22,639
of audio processing we thought well

430
00:14:20,959 --> 00:14:24,160
let's make a musical instrument and um

431
00:14:22,639 --> 00:14:25,680
because andy had the idea of making a

432
00:14:24,160 --> 00:14:27,279
theremin

433
00:14:25,680 --> 00:14:28,560
so that's so how that's how the rocklin

434
00:14:27,279 --> 00:14:29,680
came about

435
00:14:28,560 --> 00:14:31,839
so

436
00:14:29,680 --> 00:14:33,680
we start off with um with uh some foam

437
00:14:31,839 --> 00:14:34,639
moves and uh and if you want if you want

438
00:14:33,680 --> 00:14:37,120
to um

439
00:14:34,639 --> 00:14:40,800
get get a fl they run flash so that's

440
00:14:37,120 --> 00:14:42,800
basically uh flash the spi module uh

441
00:14:40,800 --> 00:14:44,480
flash memory and uh so do that initially

442
00:14:42,800 --> 00:14:46,880
by soldering some eyes on which are very

443
00:14:44,480 --> 00:14:48,320
very fine pitch and uh we managed to

444
00:14:46,880 --> 00:14:51,519
manage to do that well it was a bit

445
00:14:48,320 --> 00:14:53,760
cumbersome and so after that uh john uh

446
00:14:51,519 --> 00:14:55,440
3d printed the

447
00:14:53,760 --> 00:14:57,120
uh little test jig so you guys could

448
00:14:55,440 --> 00:15:00,160
just place the foam in the chest you can

449
00:14:57,120 --> 00:15:01,519
just flash a raspberry pi so that that

450
00:15:00,160 --> 00:15:02,800
worked

451
00:15:01,519 --> 00:15:04,720
uh and then if you wanted to actually

452
00:15:02,800 --> 00:15:07,760
play with the phone like there was um

453
00:15:04,720 --> 00:15:09,760
these four four tiny tiny pads for gpo

454
00:15:07,760 --> 00:15:11,839
so we you know sort of attached wires to

455
00:15:09,760 --> 00:15:13,600
that and the reset button that was a bit

456
00:15:11,839 --> 00:15:15,360
also a bit cumbersome but um that sort

457
00:15:13,600 --> 00:15:17,279
of gave us some confidence that

458
00:15:15,360 --> 00:15:19,040
we could build the tool chains and get

459
00:15:17,279 --> 00:15:20,560
going and uh and even though there's

460
00:15:19,040 --> 00:15:23,120
only four pins on a

461
00:15:20,560 --> 00:15:25,839
on a phone you can still create a an i2c

462
00:15:23,120 --> 00:15:27,680
bust an spi bus or even drive fpga so

463
00:15:25,839 --> 00:15:29,040
even though it's only a very tiny board

464
00:15:27,680 --> 00:15:31,120
it's um you can still have some fun with

465
00:15:29,040 --> 00:15:32,639
it

466
00:15:31,120 --> 00:15:33,680
and then from there we uh

467
00:15:32,639 --> 00:15:37,440
uh bob

468
00:15:33,680 --> 00:15:38,880
with andrew's uh nielsen's uh layout and

469
00:15:37,440 --> 00:15:41,519
bob's uh

470
00:15:38,880 --> 00:15:44,720
electronics design um we produced the

471
00:15:41,519 --> 00:15:46,320
the first prototype and uh it was a

472
00:15:44,720 --> 00:15:48,079
challenge getting that up because

473
00:15:46,320 --> 00:15:50,639
unlikely when you put a cpu down on the

474
00:15:48,079 --> 00:15:52,079
board if you it usually has an internal

475
00:15:50,639 --> 00:15:53,440
clock or if you're applying a clock

476
00:15:52,079 --> 00:15:54,880
signal it pretty much

477
00:15:53,440 --> 00:15:56,000
usually works right away or it's easy to

478
00:15:54,880 --> 00:15:58,639
diagnose

479
00:15:56,000 --> 00:16:01,279
um one of our first problems is uh

480
00:15:58,639 --> 00:16:02,560
we mistakenly chose the wrong

481
00:16:01,279 --> 00:16:05,279
uh

482
00:16:02,560 --> 00:16:08,399
internal global system clock pin to use

483
00:16:05,279 --> 00:16:10,399
and uh just nothing worked and it was um

484
00:16:08,399 --> 00:16:11,759
it was not immediately obvious how to

485
00:16:10,399 --> 00:16:13,120
you know what what the problem was but

486
00:16:11,759 --> 00:16:14,959
we uh

487
00:16:13,120 --> 00:16:16,959
eventually figured it out and uh managed

488
00:16:14,959 --> 00:16:18,480
to clock get the fpga clocking and we

489
00:16:16,959 --> 00:16:20,560
were able to um

490
00:16:18,480 --> 00:16:22,800
uh flash it and and

491
00:16:20,560 --> 00:16:24,480
and flashing a flashing led so that was

492
00:16:22,800 --> 00:16:25,440
um encouraging

493
00:16:24,480 --> 00:16:27,040
and then

494
00:16:25,440 --> 00:16:28,000
one of the

495
00:16:27,040 --> 00:16:30,320
key things you want to do is make it

496
00:16:28,000 --> 00:16:31,759
just make it easier to um

497
00:16:30,320 --> 00:16:33,519
flash and interact with the chip so

498
00:16:31,759 --> 00:16:34,720
basically put a put a has a header on

499
00:16:33,519 --> 00:16:37,040
the uh

500
00:16:34,720 --> 00:16:39,360
on the rocklin which uh gives us both

501
00:16:37,040 --> 00:16:42,320
i2c and spi so it would make it easy for

502
00:16:39,360 --> 00:16:44,240
us to uh reflash the uh the bootloader

503
00:16:42,320 --> 00:16:46,959
and also to interact with the device

504
00:16:44,240 --> 00:16:48,959
over over a sayo from the swag badge

505
00:16:46,959 --> 00:16:49,600
so you can see that's

506
00:16:48,959 --> 00:16:52,320
uh there

507
00:16:49,600 --> 00:16:53,600
once the prototype was done and uh we've

508
00:16:52,320 --> 00:16:55,360
pretty much proven out the the

509
00:16:53,600 --> 00:16:56,959
fundamental design worked we then went

510
00:16:55,360 --> 00:16:58,160
on to produce production boards and it

511
00:16:56,959 --> 00:16:59,360
was a pretty exciting day when they

512
00:16:58,160 --> 00:17:01,519
first came back because we were able to

513
00:16:59,360 --> 00:17:03,839
test uh andrew nielsen's tiling and see

514
00:17:01,519 --> 00:17:05,760
if they truly did tile the plane and we

515
00:17:03,839 --> 00:17:07,280
can make some some pretty patterns with

516
00:17:05,760 --> 00:17:09,360
them

517
00:17:07,280 --> 00:17:11,439
so so again getting down to some details

518
00:17:09,360 --> 00:17:13,679
so this is the uh

519
00:17:11,439 --> 00:17:15,120
sort of a block diagram what's going on

520
00:17:13,679 --> 00:17:16,640
inside there at the rockling so at the

521
00:17:15,120 --> 00:17:19,679
heart of it is the

522
00:17:16,640 --> 00:17:21,600
fpj and towards the uh the front of the

523
00:17:19,679 --> 00:17:23,679
uh the fish you know the the fish the

524
00:17:21,600 --> 00:17:25,360
fish head where the fish eyes that's

525
00:17:23,679 --> 00:17:26,640
that that's the analog front end for a

526
00:17:25,360 --> 00:17:29,760
theremin so

527
00:17:26,640 --> 00:17:31,520
a theremin has uh two inputs a uh a

528
00:17:29,760 --> 00:17:32,400
volume and a pitch and tennessee

529
00:17:31,520 --> 00:17:34,000
basically

530
00:17:32,400 --> 00:17:35,520
you know have moved one hand for volume

531
00:17:34,000 --> 00:17:37,520
another hand for pitch and i think

532
00:17:35,520 --> 00:17:40,799
during bob's talk later today he'll um

533
00:17:37,520 --> 00:17:43,840
he'll talk about some antenna design

534
00:17:40,799 --> 00:17:45,520
but bob took the design from open open

535
00:17:43,840 --> 00:17:47,600
thurman and so basically just translate

536
00:17:45,520 --> 00:17:48,720
that onto the onto the board and usually

537
00:17:47,600 --> 00:17:50,880
has a

538
00:17:48,720 --> 00:17:51,679
an arduino at mega chip rather than fpga

539
00:17:50,880 --> 00:17:53,760
but

540
00:17:51,679 --> 00:17:56,480
what we what we did was i see it took

541
00:17:53,760 --> 00:17:58,640
the volume and pitch uh that came from

542
00:17:56,480 --> 00:18:01,280
the front end which um should be roughly

543
00:17:58,640 --> 00:18:04,000
500 kilohertz uh and it just varies

544
00:18:01,280 --> 00:18:05,760
slightly by uh maybe 20 or 30 kilohertz

545
00:18:04,000 --> 00:18:08,559
based on your hand position

546
00:18:05,760 --> 00:18:10,160
and uh have that come into the fpga

547
00:18:08,559 --> 00:18:12,720
on the uh

548
00:18:10,160 --> 00:18:15,360
the so the rocking has both an itc bus

549
00:18:12,720 --> 00:18:17,360
for interaction with the swag badge

550
00:18:15,360 --> 00:18:18,400
and an internal i2c bus for talking to

551
00:18:17,360 --> 00:18:21,679
the

552
00:18:18,400 --> 00:18:21,679
adac which provides um

553
00:18:21,760 --> 00:18:25,280
two output folders one to act as a bias

554
00:18:24,000 --> 00:18:26,960
for the volume and other to act as a

555
00:18:25,280 --> 00:18:28,320
bias for the pitch

556
00:18:26,960 --> 00:18:30,960
and the other things on the bus is the

557
00:18:28,320 --> 00:18:32,000
uh the audio codec

558
00:18:30,960 --> 00:18:35,280
so uh

559
00:18:32,000 --> 00:18:37,520
so the fpgas i2c to control the

560
00:18:35,280 --> 00:18:40,080
dac and codec and downstream from the

561
00:18:37,520 --> 00:18:42,000
audio codec is the uh the amplifier

562
00:18:40,080 --> 00:18:43,760
so the idea is that with the fpga the

563
00:18:42,000 --> 00:18:45,760
dsps we'll be able to synthesize

564
00:18:43,760 --> 00:18:47,520
hopefully um some sophisticated sounds

565
00:18:45,760 --> 00:18:50,080
and to give that that sort of classic

566
00:18:47,520 --> 00:18:52,559
thermal noise and then over the r2c bus

567
00:18:50,080 --> 00:18:54,559
would send that data to the audio codec

568
00:18:52,559 --> 00:18:57,679
out to the amplifier then to um you know

569
00:18:54,559 --> 00:18:59,919
hit either a headphone jack or speakers

570
00:18:57,679 --> 00:19:02,080
and you can also see at the top the

571
00:18:59,919 --> 00:19:04,480
flash memories on the on the spi bus so

572
00:19:02,080 --> 00:19:06,160
that allows the swag badge to um

573
00:19:04,480 --> 00:19:07,840
initially flash

574
00:19:06,160 --> 00:19:09,440
flash the

575
00:19:07,840 --> 00:19:12,320
bootloader onto the flash memory so when

576
00:19:09,440 --> 00:19:13,440
the fpga is powered up it'll uh

577
00:19:12,320 --> 00:19:15,440
you'll

578
00:19:13,440 --> 00:19:16,559
load its bitstream from from the flash

579
00:19:15,440 --> 00:19:18,400
memory

580
00:19:16,559 --> 00:19:21,280
uh the final piece in that diagram is

581
00:19:18,400 --> 00:19:22,160
usb so there's um

582
00:19:21,280 --> 00:19:24,720
pins

583
00:19:22,160 --> 00:19:28,160
gpo pins from the fpga

584
00:19:24,720 --> 00:19:31,200
go directly to a usb connector and the

585
00:19:28,160 --> 00:19:33,600
and how that works is the

586
00:19:31,200 --> 00:19:36,400
fpga has a risc-5 processor which has a

587
00:19:33,600 --> 00:19:38,799
usb stack written in c and so when you

588
00:19:36,400 --> 00:19:40,400
power the fpg up it appears as a dfu

589
00:19:38,799 --> 00:19:41,679
device which is just a standard way of

590
00:19:40,400 --> 00:19:45,679
loading um

591
00:19:41,679 --> 00:19:47,360
firmware onto onto devices over over usb

592
00:19:45,679 --> 00:19:50,400
so

593
00:19:47,360 --> 00:19:50,400
just just to recap

594
00:19:50,480 --> 00:19:54,720
we'll provide the rockling with uh

595
00:19:52,559 --> 00:19:56,320
phobic already flashed on it but for any

596
00:19:54,720 --> 00:19:58,640
reason we need to change or reflash it

597
00:19:56,320 --> 00:20:01,200
then uh the swag badge can be used spi

598
00:19:58,640 --> 00:20:03,679
to re-flash the phone re-flash uh

599
00:20:01,200 --> 00:20:05,760
the flash memory on the on the rockling

600
00:20:03,679 --> 00:20:07,840
uh the main primary way of interacting

601
00:20:05,760 --> 00:20:11,760
between this the swag badge and the fpga

602
00:20:07,840 --> 00:20:14,240
will be via the uh sayo igc bus

603
00:20:11,760 --> 00:20:16,159
and allows the swag badge to provide a

604
00:20:14,240 --> 00:20:17,280
user interface or uh or networking for

605
00:20:16,159 --> 00:20:20,960
the rockling

606
00:20:17,280 --> 00:20:23,679
the fpga um has a little bit of gateway

607
00:20:20,960 --> 00:20:25,360
that measures the um counts the uh

608
00:20:23,679 --> 00:20:26,720
the volume and pitch

609
00:20:25,360 --> 00:20:29,280
input frequency

610
00:20:26,720 --> 00:20:31,679
and then uses um we've got a

611
00:20:29,280 --> 00:20:34,480
a soft r2c bus

612
00:20:31,679 --> 00:20:37,120
controller for controlling the dac and

613
00:20:34,480 --> 00:20:38,240
the audio codec and uh and also there's

614
00:20:37,120 --> 00:20:40,400
um

615
00:20:38,240 --> 00:20:42,000
an i2s

616
00:20:40,400 --> 00:20:45,280
module as well

617
00:20:42,000 --> 00:20:46,960
um as mentioned uh yeah the

618
00:20:45,280 --> 00:20:48,640
rocklin when you plug into usb the

619
00:20:46,960 --> 00:20:51,440
operating appears as a dfu device and

620
00:20:48,640 --> 00:20:52,880
use dfu tool to list it and then also to

621
00:20:51,440 --> 00:20:54,640
flash code

622
00:20:52,880 --> 00:20:56,559
and there's uh also it's called the

623
00:20:54,640 --> 00:20:58,400
wishbone bus so all the all the

624
00:20:56,559 --> 00:21:00,159
peripherals on the on the rockling

625
00:20:58,400 --> 00:21:02,559
appear on this 32-bit

626
00:21:00,159 --> 00:21:04,400
bus and you can just use a laptop

627
00:21:02,559 --> 00:21:05,760
command wishbone command on your laptop

628
00:21:04,400 --> 00:21:07,200
to uh interact with all those

629
00:21:05,760 --> 00:21:08,240
peripherals

630
00:21:07,200 --> 00:21:10,080
uh

631
00:21:08,240 --> 00:21:11,600
so the uh

632
00:21:10,080 --> 00:21:12,960
the phone

633
00:21:11,600 --> 00:21:15,679
normally comes with a

634
00:21:12,960 --> 00:21:17,520
a wrist five soft core that's um

635
00:21:15,679 --> 00:21:19,280
quite capable but it's also consumes

636
00:21:17,520 --> 00:21:21,200
quite a lot of resources so

637
00:21:19,280 --> 00:21:23,280
andy was able to find a

638
00:21:21,200 --> 00:21:24,960
a smaller implementation of s5 called

639
00:21:23,280 --> 00:21:28,000
arm femto

640
00:21:24,960 --> 00:21:29,039
i think femto risk and it was which um

641
00:21:28,000 --> 00:21:30,799
i gave

642
00:21:29,039 --> 00:21:33,440
didn't use quite as many uh

643
00:21:30,799 --> 00:21:35,840
logic cells so um yeah we're running out

644
00:21:33,440 --> 00:21:35,840
of room

645
00:21:35,919 --> 00:21:39,600
um yeah so

646
00:21:37,520 --> 00:21:41,200
uh during the process of um

647
00:21:39,600 --> 00:21:42,240
going to production um

648
00:21:41,200 --> 00:21:44,080
you know we have you can see there's

649
00:21:42,240 --> 00:21:46,640
lots lots of barge wires on the uh on

650
00:21:44,080 --> 00:21:48,960
the on the prototypes as uh we had to um

651
00:21:46,640 --> 00:21:50,320
use a a different pin for the system

652
00:21:48,960 --> 00:21:52,559
clock and uh

653
00:21:50,320 --> 00:21:55,440
also a ysl for testing out things like

654
00:21:52,559 --> 00:21:57,600
the usb and so on and then uh

655
00:21:55,440 --> 00:21:58,720
as as we bring each board you see

656
00:21:57,600 --> 00:22:00,880
there's like a checklist of what you

657
00:21:58,720 --> 00:22:02,400
know what things were working so to make

658
00:22:00,880 --> 00:22:04,000
sure the bootloader worked and appeared

659
00:22:02,400 --> 00:22:06,240
over usb that the

660
00:22:04,000 --> 00:22:07,520
rgb led is working to serve as just a

661
00:22:06,240 --> 00:22:10,240
this big checklist which we're still

662
00:22:07,520 --> 00:22:13,280
going through now for each of the boards

663
00:22:10,240 --> 00:22:15,200
right so um so looking at the

664
00:22:13,280 --> 00:22:16,880
the whole project the project as whole

665
00:22:15,200 --> 00:22:20,400
so the swag badge

666
00:22:16,880 --> 00:22:22,880
the uh party button and the the rockling

667
00:22:20,400 --> 00:22:25,679
this is um a bit of a an

668
00:22:22,880 --> 00:22:26,480
overview of how these all hang together

669
00:22:25,679 --> 00:22:29,280
so

670
00:22:26,480 --> 00:22:31,520
the uh the party button uh can connect

671
00:22:29,280 --> 00:22:33,520
operate stand alone i think as uh as

672
00:22:31,520 --> 00:22:34,799
john showed earlier you can uh just put

673
00:22:33,520 --> 00:22:36,799
a little uh

674
00:22:34,799 --> 00:22:39,120
baseboard that has the uh the battery

675
00:22:36,799 --> 00:22:41,679
and uh just basically short circuits the

676
00:22:39,120 --> 00:22:43,200
uh the button to the uh the mosfet so

677
00:22:41,679 --> 00:22:45,840
you just press the button and the lids

678
00:22:43,200 --> 00:22:48,320
go on but if you take that little um

679
00:22:45,840 --> 00:22:50,240
download adapter off you can

680
00:22:48,320 --> 00:22:52,480
connect the party button up as a sayo

681
00:22:50,240 --> 00:22:54,000
which then means the gpo

682
00:22:52,480 --> 00:22:56,000
input from the button or the output to

683
00:22:54,000 --> 00:22:59,200
the mosfet can then be controlled by the

684
00:22:56,000 --> 00:23:01,120
sp32 on one of the save connectors

685
00:22:59,200 --> 00:23:02,559
and uh and somebody can connect the

686
00:23:01,120 --> 00:23:06,080
rockling up to

687
00:23:02,559 --> 00:23:08,320
one of the so so we've got so one is not

688
00:23:06,080 --> 00:23:10,320
it's got not just uh rtc but also also

689
00:23:08,320 --> 00:23:12,640
the spi bus so if you put uh you can use

690
00:23:10,320 --> 00:23:14,159
that uh so connector for um

691
00:23:12,640 --> 00:23:16,000
flashing the uh

692
00:23:14,159 --> 00:23:17,760
the the rocklin from the swag badge if

693
00:23:16,000 --> 00:23:19,600
you need to otherwise would normally put

694
00:23:17,760 --> 00:23:20,880
it on a say three

695
00:23:19,600 --> 00:23:22,960
uh on the right hand side of the rock

696
00:23:20,880 --> 00:23:25,840
rocklin of the sorry the swag badge and

697
00:23:22,960 --> 00:23:28,320
that's um provides an itc bus for

698
00:23:25,840 --> 00:23:30,320
interacting with the fpga and also the

699
00:23:28,320 --> 00:23:32,559
gpo is used for the uh for resetting the

700
00:23:30,320 --> 00:23:33,840
fpga and listening to the configuration

701
00:23:32,559 --> 00:23:36,240
done

702
00:23:33,840 --> 00:23:38,320
uh pin and then finally on the rocklin

703
00:23:36,240 --> 00:23:39,120
also has the the usb connector for you

704
00:23:38,320 --> 00:23:41,840
know

705
00:23:39,120 --> 00:23:45,279
doing development from your laptop

706
00:23:41,840 --> 00:23:46,400
so uh those the swag badges for sales

707
00:23:45,279 --> 00:23:48,640
the swag badge provides the user

708
00:23:46,400 --> 00:23:50,480
interface and uh you can also provide

709
00:23:48,640 --> 00:23:52,080
additional program control monitoring

710
00:23:50,480 --> 00:23:53,279
and also the networking

711
00:23:52,080 --> 00:23:54,159
and

712
00:23:53,279 --> 00:23:56,080
we

713
00:23:54,159 --> 00:23:58,720
wanted to have the uh the party button

714
00:23:56,080 --> 00:24:00,320
so as a as a server

715
00:23:58,720 --> 00:24:02,400
we always like to give people the

716
00:24:00,320 --> 00:24:04,000
opportunity to learn to solder and also

717
00:24:02,400 --> 00:24:05,919
get a simple introduction to making sews

718
00:24:04,000 --> 00:24:07,760
whereas this is the button

719
00:24:05,919 --> 00:24:09,919
in a mosfet out

720
00:24:07,760 --> 00:24:12,480
and some of the simple ideas

721
00:24:09,919 --> 00:24:14,240
is to basically allow the uh swag badge

722
00:24:12,480 --> 00:24:16,240
to provide more more complex behavior

723
00:24:14,240 --> 00:24:18,080
than just a button controlling leads or

724
00:24:16,240 --> 00:24:20,559
maybe just networking and connect a

725
00:24:18,080 --> 00:24:22,559
couple of party buttons up together

726
00:24:20,559 --> 00:24:23,679
so um

727
00:24:22,559 --> 00:24:26,559
finally just to talking about the

728
00:24:23,679 --> 00:24:28,240
rockling the um primary may we intend

729
00:24:26,559 --> 00:24:31,760
the rock can be used with the swag

730
00:24:28,240 --> 00:24:33,919
badges are using this r2c bus where the

731
00:24:31,760 --> 00:24:35,840
esp32 is the rtc controller and the

732
00:24:33,919 --> 00:24:38,159
rocklin is the peripheral

733
00:24:35,840 --> 00:24:39,760
and we've got the two pins for our gpo

734
00:24:38,159 --> 00:24:41,600
pins for resetting and checking the

735
00:24:39,760 --> 00:24:43,360
configurations done

736
00:24:41,600 --> 00:24:44,240
and then we've also got the other header

737
00:24:43,360 --> 00:24:47,120
for the

738
00:24:44,240 --> 00:24:49,520
spo pins flashing and then on on your

739
00:24:47,120 --> 00:24:50,640
laptop you'd use uh

740
00:24:49,520 --> 00:24:52,720
when um

741
00:24:50,640 --> 00:24:55,039
we've provide instructions on how to use

742
00:24:52,720 --> 00:24:58,159
um symbiflow and set up the tool chain

743
00:24:55,039 --> 00:25:00,480
for the for um creating uh

744
00:24:58,159 --> 00:25:04,159
an fpga bitstream you suggest you just

745
00:25:00,480 --> 00:25:04,159
go you simply just type make and it uh

746
00:25:04,799 --> 00:25:08,320
basically runs all the python code and

747
00:25:06,799 --> 00:25:09,760
uh live text for

748
00:25:08,320 --> 00:25:11,200
for creating the uh the bit stream and

749
00:25:09,760 --> 00:25:14,960
you just then just use

750
00:25:11,200 --> 00:25:16,080
usual just to flash that onto the fpga

751
00:25:14,960 --> 00:25:18,159
um

752
00:25:16,080 --> 00:25:20,320
yep still got five minutes so um

753
00:25:18,159 --> 00:25:22,640
that's a quick quick run through so okay

754
00:25:20,320 --> 00:25:24,720
what sort of questions do we have like

755
00:25:22,640 --> 00:25:26,559
did any of that make sense i'm just

756
00:25:24,720 --> 00:25:28,320
jumping back in

757
00:25:26,559 --> 00:25:29,840
to pass through some questions that came

758
00:25:28,320 --> 00:25:33,039
in in the chat

759
00:25:29,840 --> 00:25:35,360
so um the first question and other

760
00:25:33,039 --> 00:25:37,760
people can chime in with this as well is

761
00:25:35,360 --> 00:25:39,679
do you have any real world problems for

762
00:25:37,760 --> 00:25:42,799
when you use an fpga versus a

763
00:25:39,679 --> 00:25:43,840
traditional mcu and why

764
00:25:42,799 --> 00:25:46,480
um

765
00:25:43,840 --> 00:25:48,720
well um

766
00:25:46,480 --> 00:25:50,480
in in a situation we have uh lots of

767
00:25:48,720 --> 00:25:52,400
parallel inputs uh where we need to do

768
00:25:50,480 --> 00:25:55,039
signal processing as a classic a classic

769
00:25:52,400 --> 00:25:57,279
use for an fpga so um

770
00:25:55,039 --> 00:25:58,960
it's it's one thing to um

771
00:25:57,279 --> 00:26:00,720
look after a small number of inputs

772
00:25:58,960 --> 00:26:01,840
through a microcontroller but if you had

773
00:26:00,720 --> 00:26:04,720
like um

774
00:26:01,840 --> 00:26:06,320
you know like a 100 100 signals that you

775
00:26:04,720 --> 00:26:08,960
need to look at simultaneously then an

776
00:26:06,320 --> 00:26:10,480
fpga would be ideal for that

777
00:26:08,960 --> 00:26:11,440
another situation people looking at is

778
00:26:10,480 --> 00:26:12,880
uh

779
00:26:11,440 --> 00:26:16,159
with um

780
00:26:12,880 --> 00:26:18,240
uh with cmos transistors whenever you um

781
00:26:16,159 --> 00:26:19,919
change state that consumes power if

782
00:26:18,240 --> 00:26:21,120
you're not if the transistor is not not

783
00:26:19,919 --> 00:26:23,520
not switching

784
00:26:21,120 --> 00:26:25,600
um it doesn't use any power so with an

785
00:26:23,520 --> 00:26:27,600
fpga you can have you know minimize the

786
00:26:25,600 --> 00:26:29,120
number of transistors to just what you

787
00:26:27,600 --> 00:26:31,039
need so for people who are playing with

788
00:26:29,120 --> 00:26:32,559
neural networks where they only need um

789
00:26:31,039 --> 00:26:34,799
a single bit they don't need eight bit

790
00:26:32,559 --> 00:26:35,840
or four thirty bit numbers uh applying

791
00:26:34,799 --> 00:26:38,559
an

792
00:26:35,840 --> 00:26:40,960
fpga to um small neural networks to save

793
00:26:38,559 --> 00:26:42,559
power is another another option

794
00:26:40,960 --> 00:26:45,279
okay

795
00:26:42,559 --> 00:26:47,039
next question is will fpga save us from

796
00:26:45,279 --> 00:26:50,840
the component shortage apocalypse and

797
00:26:47,039 --> 00:26:54,799
replace hard to buy ic ip with an

798
00:26:50,840 --> 00:26:56,720
fpga well well perhaps um

799
00:26:54,799 --> 00:26:58,400
uh that

800
00:26:56,720 --> 00:27:00,559
uh as a bit of an aside

801
00:26:58,400 --> 00:27:02,559
as uh companies like apple and i think

802
00:27:00,559 --> 00:27:04,799
also tesla doing the same thing where

803
00:27:02,559 --> 00:27:07,440
they they um

804
00:27:04,799 --> 00:27:09,760
incomp control their complete tech stack

805
00:27:07,440 --> 00:27:11,600
and so in contrast to other car

806
00:27:09,760 --> 00:27:13,840
manufacturers when there was a chip

807
00:27:11,600 --> 00:27:15,600
shortage tess was able to

808
00:27:13,840 --> 00:27:16,880
get different chips and just rewrite

809
00:27:15,600 --> 00:27:18,480
their software stack to use those

810
00:27:16,880 --> 00:27:20,320
different ships whereas if

811
00:27:18,480 --> 00:27:22,320
other companies like gm and so on we

812
00:27:20,320 --> 00:27:23,760
were dependent upon other third parties

813
00:27:22,320 --> 00:27:24,880
they were they were stuffed they if they

814
00:27:23,760 --> 00:27:26,880
couldn't get the chips they needed they

815
00:27:24,880 --> 00:27:28,960
couldn't change the software

816
00:27:26,880 --> 00:27:31,840
so um in a situation where you could do

817
00:27:28,960 --> 00:27:33,440
control your whole stack

818
00:27:31,840 --> 00:27:34,640
and you can have like an fpga and you

819
00:27:33,440 --> 00:27:35,840
can um

820
00:27:34,640 --> 00:27:38,799
uh

821
00:27:35,840 --> 00:27:40,640
change it to um to for your needs and um

822
00:27:38,799 --> 00:27:42,559
then then perhaps

823
00:27:40,640 --> 00:27:43,840
and this is on the um

824
00:27:42,559 --> 00:27:45,840
the optimistic

825
00:27:43,840 --> 00:27:48,240
side of things where the fpgas

826
00:27:45,840 --> 00:27:49,840
themselves remain available yes which is

827
00:27:48,240 --> 00:27:51,600
difficult as well

828
00:27:49,840 --> 00:27:53,039
um but i certainly like the idea that if

829
00:27:51,600 --> 00:27:53,840
you've got um

830
00:27:53,039 --> 00:27:55,520
uh

831
00:27:53,840 --> 00:27:57,679
you basically need a cpu and you've got

832
00:27:55,520 --> 00:28:00,080
some other logic other digital logic

833
00:27:57,679 --> 00:28:01,919
that um to be able to you know integrate

834
00:28:00,080 --> 00:28:03,279
that onto a single chip is a nice thing

835
00:28:01,919 --> 00:28:04,399
and if you do need to make some simple

836
00:28:03,279 --> 00:28:06,960
changes you don't have to go and buy a

837
00:28:04,399 --> 00:28:08,399
new you know a different different um

838
00:28:06,960 --> 00:28:10,640
say small scale integration chips you

839
00:28:08,399 --> 00:28:12,799
just simply change your fpga that's

840
00:28:10,640 --> 00:28:14,159
that's a certainly a nice thing so i

841
00:28:12,799 --> 00:28:15,440
think we saw that in the early days of

842
00:28:14,159 --> 00:28:17,760
them

843
00:28:15,440 --> 00:28:19,679
hobbyist pcs where um

844
00:28:17,760 --> 00:28:22,080
the first um apples and other things

845
00:28:19,679 --> 00:28:23,520
where they maybe use 20 or 30 or 40

846
00:28:22,080 --> 00:28:24,880
chips and you look at something like an

847
00:28:23,520 --> 00:28:26,799
apple two gs and there's only like six

848
00:28:24,880 --> 00:28:29,440
chips and so

849
00:28:26,799 --> 00:28:30,880
um increasing your integration is always

850
00:28:29,440 --> 00:28:32,399
a good thing

851
00:28:30,880 --> 00:28:34,799
also a question specifically about the

852
00:28:32,399 --> 00:28:37,520
rockling is can we use the rockling to

853
00:28:34,799 --> 00:28:38,480
do stuff even if we don't touch the fpga

854
00:28:37,520 --> 00:28:40,720
at all

855
00:28:38,480 --> 00:28:41,760
yes great question you can because the

856
00:28:40,720 --> 00:28:43,760
um

857
00:28:41,760 --> 00:28:45,440
the first way you can start to use the

858
00:28:43,760 --> 00:28:48,559
rockling is simply as a risk five

859
00:28:45,440 --> 00:28:49,600
processor that um has uh the peripherals

860
00:28:48,559 --> 00:28:52,080
the

861
00:28:49,600 --> 00:28:54,159
i2c control and peripherals the uh the

862
00:28:52,080 --> 00:28:55,919
dac and the auto codec and and it's just

863
00:28:54,159 --> 00:28:58,240
there's a c code

864
00:28:55,919 --> 00:29:00,399
there's initializing these peripherals

865
00:28:58,240 --> 00:29:02,000
and then i'm sending um i2c

866
00:29:00,399 --> 00:29:03,120
commands to um

867
00:29:02,000 --> 00:29:04,799
set the

868
00:29:03,120 --> 00:29:07,200
the the dac is really used to use it's

869
00:29:04,799 --> 00:29:09,840
basically a one command to

870
00:29:07,200 --> 00:29:11,679
set the the the voltage for um

871
00:29:09,840 --> 00:29:13,760
one channel so there are two commands

872
00:29:11,679 --> 00:29:15,840
you can change the voltages on the two

873
00:29:13,760 --> 00:29:17,279
channels for the front at the front end

874
00:29:15,840 --> 00:29:18,720
uh the audio codec is a little bit more

875
00:29:17,279 --> 00:29:20,000
complex to um

876
00:29:18,720 --> 00:29:22,080
control which they're still going

877
00:29:20,000 --> 00:29:24,000
through that but um it takes a series of

878
00:29:22,080 --> 00:29:26,399
i2c commands to stop the inputs the

879
00:29:24,000 --> 00:29:27,279
outputs the

880
00:29:26,399 --> 00:29:28,480
uh

881
00:29:27,279 --> 00:29:30,559
the um

882
00:29:28,480 --> 00:29:32,799
the clock the clock rates for the i2c

883
00:29:30,559 --> 00:29:34,960
bus sorry sorry the i2s bus and so on

884
00:29:32,799 --> 00:29:36,960
and west uh but that is all just um c

885
00:29:34,960 --> 00:29:38,320
code that we're changing on top of the

886
00:29:36,960 --> 00:29:41,440
fpga

887
00:29:38,320 --> 00:29:42,960
okay and um one final question which i

888
00:29:41,440 --> 00:29:44,960
think is a very interesting one what

889
00:29:42,960 --> 00:29:46,960
would it take to expose the fpga

890
00:29:44,960 --> 00:29:49,679
wishbone bus as an external memory

891
00:29:46,960 --> 00:29:53,360
device to the esp host processor eg

892
00:29:49,679 --> 00:29:55,440
memory mapped gateway peripherals

893
00:29:53,360 --> 00:29:57,600
okay

894
00:29:55,440 --> 00:30:00,720
um let me think about a sec

895
00:29:57,600 --> 00:30:01,600
so the um the wishbone bus allows you to

896
00:30:00,720 --> 00:30:04,880
wrap

897
00:30:01,600 --> 00:30:06,159
any um any peripheral as a uh in the

898
00:30:04,880 --> 00:30:10,880
fpga

899
00:30:06,159 --> 00:30:13,120
as a as a uh uh on a on a 32 address and

900
00:30:10,880 --> 00:30:15,279
so what we could potentially do is um

901
00:30:13,120 --> 00:30:18,080
and i'm really making this up on the fly

902
00:30:15,279 --> 00:30:22,320
is uh we we communicate between the the

903
00:30:18,080 --> 00:30:25,520
esp32 is the i2 i2c um controller of bus

904
00:30:22,320 --> 00:30:26,640
zero and the fpga as the peripheral and

905
00:30:25,520 --> 00:30:28,000
so

906
00:30:26,640 --> 00:30:30,240
um

907
00:30:28,000 --> 00:30:31,120
if we had um

908
00:30:30,240 --> 00:30:32,880
uh

909
00:30:31,120 --> 00:30:34,640
the uh well actually we already do have

910
00:30:32,880 --> 00:30:36,880
the ability for understanding

911
00:30:34,640 --> 00:30:37,840
wishbone commands that um right to the

912
00:30:36,880 --> 00:30:39,760
um

913
00:30:37,840 --> 00:30:41,760
the to the i2c bus

914
00:30:39,760 --> 00:30:42,799
um yeah i'd say i'd say potentially

915
00:30:41,760 --> 00:30:45,440
possible to

916
00:30:42,799 --> 00:30:48,240
use wishbone commands to um talk talk to

917
00:30:45,440 --> 00:30:49,440
the rtc bus with the esp32 so we'll take

918
00:30:48,240 --> 00:30:50,960
a little bit of work but i can see it's

919
00:30:49,440 --> 00:30:52,640
it's possible

920
00:30:50,960 --> 00:30:54,000
um i said that was a final question but

921
00:30:52,640 --> 00:30:56,159
there is actually one more that was in

922
00:30:54,000 --> 00:30:58,320
the chat unfortunately we have to answer

923
00:30:56,159 --> 00:31:00,399
no the question was can we have a

924
00:30:58,320 --> 00:31:02,720
performance of the theremin

925
00:31:00,399 --> 00:31:04,720
and unfortunately it's not quite at that

926
00:31:02,720 --> 00:31:06,320
functional point there has been

927
00:31:04,720 --> 00:31:08,000
validation of various parts of the

928
00:31:06,320 --> 00:31:10,240
circuit but we do not have the complete

929
00:31:08,000 --> 00:31:13,600
working system so things like the

930
00:31:10,240 --> 00:31:15,919
oscillators in the analog front end that

931
00:31:13,600 --> 00:31:18,240
read from the antennas to measure your

932
00:31:15,919 --> 00:31:19,840
hand position and those sorts of things

933
00:31:18,240 --> 00:31:21,279
there's been some testing done of those

934
00:31:19,840 --> 00:31:22,640
and we can see on the oscilloscope that

935
00:31:21,279 --> 00:31:24,159
the signal coming out of them makes

936
00:31:22,640 --> 00:31:25,360
sense oh and better than that we've

937
00:31:24,159 --> 00:31:29,519
actually got the fpga is actually

938
00:31:25,360 --> 00:31:31,840
counting the uh the frequency so um

939
00:31:29,519 --> 00:31:36,399
uh there's a couple of um diagnostic

940
00:31:31,840 --> 00:31:37,679
tools uh one is one allows you to um

941
00:31:36,399 --> 00:31:40,159
reference uh

942
00:31:37,679 --> 00:31:42,240
the um or actually

943
00:31:40,159 --> 00:31:46,399
let's say so again the rom and the ram

944
00:31:42,240 --> 00:31:48,080
of the risc-5 cpu is uh mapped onto the

945
00:31:46,399 --> 00:31:50,159
whisper bus and so you can actually get

946
00:31:48,080 --> 00:31:51,279
the um when you compile the c code for

947
00:31:50,159 --> 00:31:54,000
the risk five you can actually get the

948
00:31:51,279 --> 00:31:55,279
memory map of the uh the various um c

949
00:31:54,000 --> 00:31:57,200
variables and so you can actually just

950
00:31:55,279 --> 00:31:58,960
on the wishbone bus look at those and so

951
00:31:57,200 --> 00:32:00,159
you can actually see the c code that's

952
00:31:58,960 --> 00:32:03,360
the c variable it's actually counting

953
00:32:00,159 --> 00:32:04,559
the frequency so there's that way um and

954
00:32:03,360 --> 00:32:06,240
so yes we've actually we've seen that

955
00:32:04,559 --> 00:32:08,320
it's i'm correctly counting the um the

956
00:32:06,240 --> 00:32:09,919
theorem input what we haven't got um

957
00:32:08,320 --> 00:32:11,120
fully going is the

958
00:32:09,919 --> 00:32:13,279
uh

959
00:32:11,120 --> 00:32:15,200
there's five processor on the fpga

960
00:32:13,279 --> 00:32:17,679
seeing the right i2c commands to set up

961
00:32:15,200 --> 00:32:20,159
the uh the audio codec

962
00:32:17,679 --> 00:32:21,519
by which we get sound out yeah and uh

963
00:32:20,159 --> 00:32:23,760
we're we're pretty much out of time

964
00:32:21,519 --> 00:32:25,200
we're a minute or two over time now

965
00:32:23,760 --> 00:32:27,600
but there was one question which is how

966
00:32:25,200 --> 00:32:29,039
many times can you reflash these things

967
00:32:27,600 --> 00:32:31,120
and then i think we're gonna have to

968
00:32:29,039 --> 00:32:31,919
wrap it up um

969
00:32:31,120 --> 00:32:34,240
uh

970
00:32:31,919 --> 00:32:36,799
the we're using a standard um flash

971
00:32:34,240 --> 00:32:38,080
memory module so um

972
00:32:36,799 --> 00:32:43,159
you could uh

973
00:32:38,080 --> 00:32:43,159
re-flash it thousands of times yeah

974
00:32:45,519 --> 00:32:48,640
anytime soon

975
00:32:46,799 --> 00:32:49,840
okay okay well i hope that was useful

976
00:32:48,640 --> 00:32:51,760
made sense it was a little bit a little

977
00:32:49,840 --> 00:32:54,000
bit of a rush but um thank you for

978
00:32:51,760 --> 00:32:55,600
listening and uh we're looking forward

979
00:32:54,000 --> 00:32:57,919
to getting this some in in your hands

980
00:32:55,600 --> 00:32:59,840
and and collaborating on on some

981
00:32:57,919 --> 00:33:02,240
building some stuff yeah so in a couple

982
00:32:59,840 --> 00:33:04,480
of minutes we will be back at 2 40 p.m

983
00:33:02,240 --> 00:33:06,559
um tisha will be talking about open

984
00:33:04,480 --> 00:33:08,960
hardware where the radar awesome thank

985
00:33:06,559 --> 00:33:11,840
you very much and uh we'll see you soon

986
00:33:08,960 --> 00:33:11,840
okay thanks